PUF-derived secure storage for an SoC subsystem
The SEC module is an APB-attached secure storage subsystem integrated next to a RISC-V core on the Edu4Chip teaching System-on-Chip. Software provides plaintext records through a register interface; the hardware stores authenticated ciphertext in external flash. The 128-bit encryption key is not stored in non-volatile memory. Instead, it is reconstructed at boot from an SRAM PUF response and public helper data. This site summarizes the architecture, software interface, implementation trade-offs, and verification results.
Motivation
Embedded systems often need to protect data stored outside the trusted digital logic. Storing a long-term key directly in flash or fuses creates a fixed extraction target. This project evaluates a different approach: derive the key from an SRAM PUF at boot, stabilize it with error correction, and use ASCON authenticated encryption before any record is written to external memory. The flash stores ciphertext, authentication metadata, and public helper data, but not the reconstructed key.
Avoid persistent secret storage
Long-term keys in non-volatile memory increase the impact of physical readout or firmware-level exposure.
Reconstruct the key at boot
An SRAM PUF and BCH-based correction recover a stable 128-bit key from device-specific startup behavior and public helper data.
Authenticated encrypted records
Each 256-byte flash page contains associated data, ciphertext, and an ASCON tag. Modified records are rejected during read-back.
System Overview
The subsystem connects a firmware-visible APB interface to a hardware-controlled data path. The Main FSM coordinates the ASCON core, nonce counter, fuzzy extractor, FIFOs, and Quad-SPI master. Plaintext enters only through the APB-side write path, while external flash stores authenticated encrypted records and provisioning data.
Reading the colours: ■ plaintext / APB · ■ ciphertext · ■ metadata, counters, helper data · ■ key material, tags, control
Explore the documentation
Each section can be read independently. Start with the data path for a system view, or use the references for implementation details.
Encrypt & Decrypt →
Step-by-step view of how APB writes become authenticated encrypted flash records, and how reads are checked before release.
animatedStartup & Enrollment →
How the SRAM PUF response, BCH correction, and helper data produce a reproducible key at each power-up.
interactiveMain FSM →
An interactive map of the 47-state controller covering boot, enrollment, reconstruction, write, read, and error paths.
animatedFlash & QSPI →
The Quad-SPI protocol used to initialize, program, erase, and read the external W25Q64JV flash.
referenceRegisters & Commands →
Firmware-facing register map, bit fields, error codes, and example access sequences.
referenceVerification →
Simulation, assertion, and FPGA evidence used to evaluate the implementation.
blogImplementation Challenges →
Selected implementation issues, root causes, and design changes that affected the final architecture.
Key parameters
Contributors
Designed, implemented, and verified by four M.Sc. students at TUM. For questions about the module, RTL, or documentation, contact the project contributors below.